The present invention relates to semiconductor device technology and more particularly to Quasi-Accumulation Mode Power Field Effect Transistors (QAMFETs).
The gallium arsenide (GaAs) metal Schottky barrier field effect transistor (MESFET) has been known since 1964 and is now in widespread use. In normal MESFET operation the gate contact is biased negative with respect to the source contact and electron current flows from a source region to a drain region via an active channel disposed under a gate. At maximum negative potential the electrons under the gate are driven (repelled) away from the gate and pinch-off of the flow of electrons (current) from the source to the drain edge of the device occurs. As the negative gate potential is decreased, electrons flow from the source through the active channel to the drain edge producing current flow. This is called depletion mode operation. When the gate is biased positive with respect to the source in a normal MESFET many of the electrons from the source edge of the GaAs channel are collected by the gate and current flow from source to drain is reduced. For a given gate voltage the channel current flow increases as the drain voltage increases. Eventually, for sufficiently large drain voltages, the current will saturate. Voltage breakdown on the drain edge of the control gate occurs at a larger voltage. Thus a significant limitation of the GaAs MESFET is its inability to handle large voltages without experiencing voltage breakdown on the drain edge of the control gate. Another limitation is the self-depletion of charge carriers just beneath the upper surface of the active channel as a result of mid-gap Fermi level pinning associated with large surface state densities of fixed charge.
To overcome the self-depletion of charge problem, manufacturers of GaAs power MESFETs have generally resorted to the fabrication of active channel layers much thicker than required for optimum device performance. These channels are then etched back in their centers until the saturated source-drain current value is acceptable. A Schottky control gate is then deposited in the etched-back mid channel region. The procedure is known as recessed gate technology and has become the industry standard. FIG. 1 is a schematic crosssection diagram of a prior art MESFET 10 device manufactured according to this process. The MESFET is provided with an n-Type recessed GaAs Epitaxial channel 12, a source contact 14, a metal gate 16 and a drain contact 18 grown in order on a semi-insulating GaAs substrate 20.
Fabrication by the recessed gate technology is cumbersome and does not lend itself to high yield, integrated circuit fabrication as the etch-back must be carefully done under electrical bias in a wet chemical solution. The result is a very non-planar surface.